VHDL Design

A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output. In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mealy_1011 is     Port ( W, clk, reset : in  STD_LOGIC;            z : out  STD_LOGIC); end Mealy_1011; architecture Behavioral of Mealy_1011 is type state_type is (a,b,c,d); signal Y : state_type; begin process(clk,reset) begin if(reset ='1') then Y <= A; ELSIF(RISING_EDGE(CLK)) THEN CASE Y IS WHEN A => IF(W='0') THEN y <= A; z <= '0

In PISO type shift register, the data is given as input to all the flip-flops at the same time (simultaneously), and the circuit will produce the serial output. In the VHDL Code Pin: Parallel Input CLR: clear input (or RESET input) CLK: clock input L_S: Load/Shift signal, used to control whether to load the Shift register with new data on Pin (i.e. L_S='1')  or to shift the existing data in the Shift register (i.e. L_S='0'). Sout: Output Signal VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Left_SR is     Port ( Pin : in  STD_LOGIC_VECTOR (7 downto 0);            clr, clk, L_S : in  STD_LOGIC;            sout : out  STD_LOGIC); end Left_SR; architecture Behavioral of Left_SR is signal temp: std_logic_vector(7 downto 0); begin process(clk,clr) begin if(clr='1') then temp <= "00000000"; elsif (clk'event and clk='1') then if(L_S='1') then temp <= pin; else  temp <= temp(6

In digital design, a counter is a device which stores the number of times a particular event has occurred, often with respect to a clock signal. The most common type is a sequential digital logic circuit with an input line called the clock and multiple output lines representing the count. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity U_DCOUNTER is     Port ( RESET : in  STD_LOGIC;            U_D : in  STD_LOGIC;            CLK : in  STD_LOGIC;            Cout : out  STD_LOGIC_VECTOR (3 downto 0)); end U_DCOUNTER; architecture U_DCOUNTER of U_DCOUNTER is begin process(CLK,RESET) variable temp:STD_LOGIC_VECTOR (3 downto 0):="0000"; begin if (RESET='1')then temp:="0000"; elsif(CLK'event and CLK='1'

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If the T input is high, the T flip-flop changes state (i.e. toggles) whenever the clock input is applied. If the T input is low, the flip-flop holds the previous value. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity T_FF is     Port ( T : in  STD_LOGIC;            clk : in  STD_LOGIC;            Q : out  STD_LOGIC;            rst : in  STD_LOGIC); end T_FF; architecture Behavioral of T_FF is signal temp : std_logic; begin process(clk,rst,t) begin if (rst='1') then temp <= '0'; elsif(clk'event and clk ='1') then if(T='1') then temp <= not temp; end if; end if; end process; Q <= temp; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY T_FF_tb IS END T_FF_tb;   ARCHITECTURE behavior OF T_FF_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT T_FF     PORT(          T : IN  std_logic;          clk : IN  std_logic;          Q : OU

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store 1-bit of information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. The D flip-flop, which is widely used, also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge or falling edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FF is     Port ( D : in  STD_LOGIC;            clk : in  STD_LOGIC;            Q : out  STD_LOGIC); end D_FF; architecture Behavioral of D_FF is begin process begin --if (clk'event and clk='1') then wait until clk'event and clk='1';     -- additionally comm

The output of a priority encoder is the binary representation of the index of the most significant activated line, starting from zero. They are often used to control interrupt requests by acting on the highest priority interrupt input. If two or more inputs are given at the same time, the input having the highest priority will take precedence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Priority_encode is port(I : in std_logic_vector(3 downto 0); Y : out std_logic_vector(1 downto 0); P : out std_logic); end Priority_encode; architecture Behavioral of Priority_encode is begin P <= I(0) or I(1) or I(2) or I(3); Y <= "11" when I(3) = '1' else "10" when I(2) = '1' else "01" when I(1) = '1' else "00" when I(0) = '1' else "ZZ"; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY PE_tb IS END PE_tb;   ARCHITECTURE behavior OF PE_tb I

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Compare_4 is     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);            B : in  STD_LOGIC_VECTOR (3 downto 0);            Eq : out  STD_LOGIC;            Gt : out  STD_LOGIC;            Lt : out  STD_LOGIC); end Compare_4; architecture Behavioral of Compare_4 is begin process (a,b) is     begin         if (a=b) then             eq <= '1';             gt <= '0';             lt <= '0';         elsif (a<b) then             eq <= '0';             gt <= '0';             lt <= '1';         else             eq <= '0';             gt <= '1';             lt <= '0';         end if;     end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY compare_4_tb IS END compare_4_tb;   ARCHITECTURE behavior OF compare_4_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT Compa

Comparator circuit is used to compare two input signals and generates signals accordingly. The 4-bit comparator circuit compares two 4-bit numbers and generates 1-bit signals less than(Lt), greater than(Gt) or equal to(Eq). Irrespective of size of input numbers being compared the output signals remains the same. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity compare_4 is     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);            B : in  STD_LOGIC_VECTOR (3 downto 0);            Eq : out  STD_LOGIC;            Gt : out  STD_LOGIC;            Lt : out  STD_LOGIC); end compare_4; architecture Behavioral of compare_4 is begin Eq <= '1' WHEN A = B ELSE '0' ; Gt <= '1' WHEN A > B ELSE '0' ; Lt <= '1' WHEN A < B ELSE '0' ; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Compare_4_tb IS END Compare_4_tb;   ARCHITECTURE behavior OF Compare_4_tb IS        -- Component Declaration for

A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^n unique outputs.  VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder38 is     Port ( A : in  STD_LOGIC_VECTOR(2 downto 0);            G1,G2b,G3b : in  STD_LOGIC;            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end decoder38; architecture Behavioral of decoder38 is signal en : std_logic_vector (5 downto 0) ; begin en <= (G1 & G2b & G3b) & A ; with en select  y <= "00000001" when "100000", "00000010" when "100001", "00000100" when "100010", "00001000" when "100011", "00010000" when "100100", "00100000" when "100101", "01000000" when "100110", "10000000" when "100111", "00000000" when others; en

The following VHDL Code is written using when-else statement. D input is permanently held logic HIGH, while select input S changes through 000 to 111, connecting D to output line Y0 to Y7 respectively. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Demux_1to8 is     Port ( D : in  STD_LOGIC;            S : in  STD_LOGIC_VECTOR (2 downto 0);            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end Demux_1to8; architecture Behavioral of Demux_1to8 is begin      Y <=  "0000000"&D   when S="000" else "000000"&D&'0'      when S="001" else "00000"&D&"00"    when S="010" else "0000"&D&"000"   when S="011" else "000"&D&"0000"   when S="100" else "00"&D&"00000"   when S="101" else '0'&D&"000000"     when S="110

The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using case-when  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Demux_14 is     Port ( Din : in  STD_LOGIC;            Sel : in  STD_LOGIC_VECTOR (1 downto 0);            dout : out  STD_LOGIC_VECTOR (3 downto 0)); end Demux_14; architecture Behavioral of Demux_14 is begin process(din,sel) begin case sel is when "11" => dout <= din&"000"; when "10" => dout <= '0'&din&"00"; when "01" => dout <= "00"&din&'0'; when others => dout <= "000"&din; end case; end process; end Behavioral; Testbench: LIBRAR

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Shift registers in digital systems are group of Flip-flops connected together to store multiple bits of data and are used to Shift the stored data to Left or Right.  The register that shifts the bits towards left (from LSb to MSb) are called Left Shift Registers and the one which shifts the bits towards right (from MSb to LSb) are called Right Shift Registers. The following VHDL code is written for 4-bit Left Shift Register which allows serial input and serial output (SISO). The design has asynchronous reset pin (rst), when active (HIGH), resets (output=0000) the Shift register. Otherwise, the design will load 1-bit data on every active edge of the clock into the register and at the same time 1-bit data output is generated. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Left_SR is     Port ( Sin : in  STD_LOGIC;            clk,rst : in  STD_LOGIC;            Sout : out  STD_LOGIC); end Left_SR; architecture Behavioral of Left_SR is signal temp : std_logic_vector(3 downt

The  4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  case-when  statement (requential statement). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_41 is     Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);            s : in  STD_LOGIC_vector(1 downto 0);            Y : out  STD_LOGIC); end Mux_41; architecture Behavioral of Mux_41 is begin process(I,s) begin case s is when "00" => Y <= I(0); when "01" => Y <= I(1); when "10" => Y <= I(2); when "11" => Y <= I(3); when others => Y <= 'Z'; end case; end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY Mux_41_tb IS END Mux_41_tb;   ARCHITECTURE behavior OF Mux_41_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT Mux_41     PORT(          I : IN  std_logic_vector(