Priority Encoder VDHL Code

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The output of a priority encoder is the binary representation of the index of the most significant activated line, starting from zero. They are often used to control interrupt requests by acting on the highest priority interrupt input.
If two or more inputs are given at the same time, the input having the highest priority will take precedence.


VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Priority_encode is
port(I : in std_logic_vector(3 downto 0);
Y : out std_logic_vector(1 downto 0);
P : out std_logic);
end Priority_encode;

architecture Behavioral of Priority_encode is

begin
P <= I(0) or I(1) or I(2) or I(3);
Y <= "11" when I(3) = '1' else
"10" when I(2) = '1' else
"01" when I(1) = '1' else
"00" when I(0) = '1' else
"ZZ";
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY PE_tb IS
END PE_tb;
 
ARCHITECTURE behavior OF PE_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Priority_encode
    PORT(
         I : IN  std_logic_vector(3 downto 0);
         Y : OUT  std_logic_vector(1 downto 0);
         P : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal I : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs
   signal Y : std_logic_vector(1 downto 0);
   signal P : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Priority_encode PORT MAP (
          I => I,
          Y => Y,
          P => P
        );

   -- Stimulus process
   stim_proc: process(I)
   begin
I(0) <= not I(0) after 10 ns;
I(1) <= not I(1) after 20 ns;
I(2) <= not I(2) after 40 ns;
I(3) <= not I(3) after 80 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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