3-to-8 line Decoder VHDL Code (with-select-when)
A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^n unique outputs.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder38 is
Port ( A : in STD_LOGIC_VECTOR(2 downto 0);
G1,G2b,G3b : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder38;
architecture Behavioral of decoder38 is
signal en : std_logic_vector (5 downto 0) ;
begin
en <= (G1 & G2b & G3b) & A ;
with en select
y <= "00000001" when "100000",
"00000010" when "100001",
"00000100" when "100010",
"00001000" when "100011",
"00010000" when "100100",
"00100000" when "100101",
"01000000" when "100110",
"10000000" when "100111",
"00000000" when others;
end Behavioral;
Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decoder38_tb IS
END decoder38_tb;
ARCHITECTURE behavior OF decoder38_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder38
PORT(
A : IN std_logic_vector(2 downto 0);
G1 : IN std_logic;
G2b : IN std_logic;
G3b : IN std_logic;
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(2 downto 0) := (others => '0');
signal G1 : std_logic := '0';
signal G2b : std_logic := '0';
signal G3b : std_logic := '0';
--Outputs
signal Y : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder38 PORT MAP (
A => A,
G1 => G1,
G2b => G2b,
G3b => G3b,
Y => Y
);
-- Stimulus process
stim_proc: process(A,G1,G2b,G3b)
begin
G1 <= '1' after 30 ns;
G2b <= '0';
G3b <= '0' after 40 ns;
A(2) <= not A(2) after 80 ns;
A(1) <= not A(1) after 40 ns;
A(0) <= not A(0) after 20 ns;
end process;
END;
Output:
Good.
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