Shift Register (Parallel-In-Serial-Out) VHDL Code

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In PISO type shift register, the data is given as input to all the flip-flops at the same time (simultaneously), and the circuit will produce the serial output.

In the VHDL Code

Pin: Parallel Input
CLR: clear input (or RESET input)
CLK: clock input
L_S: Load/Shift signal, used to control whether to load the Shift register with new data on Pin (i.e. L_S='1')  or to shift the existing data in the Shift register (i.e. L_S='0').
Sout: Output Signal

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Left_SR is
    Port ( Pin : in  STD_LOGIC_VECTOR (7 downto 0);
           clr, clk, L_S : in  STD_LOGIC;
           sout : out  STD_LOGIC);
end Left_SR;
architecture Behavioral of Left_SR is
signal temp: std_logic_vector(7 downto 0);
begin
process(clk,clr)
begin
if(clr='1') then
temp <= "00000000";
elsif (clk'event and clk='1') then
if(L_S='1') then
temp <= pin;
else 
temp <= temp(6 downto 0)&'0';
end if;
end if;
end process;
sout <= temp(7);
end Behavioral;


Testbench:

   -- Stimulus process
   stim_proc: process
   begin
      Pin<= "10000000";
clr <= '1';
wait for 10 ns;
Pin<= "00000001";
clr <= '0';
L_S <= '1';
wait for 10 ns;
clr <= '0';
L_S <= '0';
wait for 160 ns;
   end process;
END;

(Only Stimulus process is given here)


Output:


In this waveform, at 15ns, the new data on 'Pin" gets loaded into the shift register. After this, with L_S='0', data shift starts. At 85ns, (i.e. 8th clock cycle after L_S='1') the data will be available at output 'Sout'.


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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