8-TO-1 Multiplexer VHDL Code (Structural Style)

In electronics Multiplexer (also called MUX) is a circuit that has several inputs and one output line. The output depends on the select line input signal.

In the following example the 8-to-1 MUX is written in structural modelling style while the components which are used in design are written with behavioral style. (4-to-1 MUX is written using sequential statement case-when while 2-to-1 MUX is written using concurrent statement when-else.)

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_81 is
    Port ( D : in  STD_LOGIC_VECTOR (7 downto 0);
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           Y : out  STD_LOGIC);
end Mux_81;
architecture Behavioral of Mux_81 is
signal y1,y2 : std_logic;
component Mux_41 is
port(I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
end component;
component Mux_21 is
port (I0,I1,S : in std_logic;
Y : out std_logic);
end component;
begin
M1 : Mux_41 port map (I(0)=>D(0),I(1)=>D(1),I(2)=>D(2),I(3)=>D(3),S(1)=>S(1),S(0)=>S(0),Y=>y1);
M2 : Mux_41 port map (I(0)=>D(4),I(1)=>D(5),I(2)=>D(6),I(3)=>D(7),S(1)=>S(1),S(0)=>S(0),Y=>y2);
M3 : Mux_21 port map (y1,y2,S(2),Y);
end Behavioral;

VHDL Code of 4-to-1 MUX:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41 is
    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_vector(1 downto 0);
           Y : out  STD_LOGIC);
end Mux_41;
architecture Behavioral of Mux_41 is
begin
process(I,s)
begin
case s is
when "00" => Y <= I(0);
when "01" => Y <= I(1);
when "10" => Y <= I(2);
when "11" => Y <= I(3);
when others => Y <= 'Z';
end case;
end process;
end Behavioral;

VHDL Code for 2-to-1 MUX:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Mux_21 is

    Port ( I0 : in  STD_LOGIC;

           I1 : in  STD_LOGIC;

           S : in  STD_LOGIC;

           Y : out  STD_LOGIC);

end Mux_21;

architecture Behavioral of Mux_21 is

begin

Y <= I0 when s = '0' else

 I1 when s = '1' else

 'Z';

end Behavioral;

Testbench:

Testbench is written for 8-to-1 MUX only. (As 4-to-1 MUX and 2-to-1 MUX are already tested)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Mux_81_tb IS
END Mux_81_tb;
 
ARCHITECTURE behavior OF Mux_81_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Mux_81
    PORT(
         D : IN  std_logic_vector(7 downto 0);
         S : IN  std_logic_vector(2 downto 0);
         Y : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal D : std_logic_vector(7 downto 0) := (others => '0');
   signal S : std_logic_vector(2 downto 0) := (others => '0');
  --Outputs
   signal Y : std_logic;
 
BEGIN
 --Instantiate the Unit Under Test (UUT)
   uut: Mux_81 PORT MAP (
          D => D,
          S => S,
          Y => Y
        );
   -- Stimulus process
   stim_proc: process(D,S)
   begin
D <= "01010101";
S(2) <= not S(2) after 80 ns;
S(1) <= not S(1) after 40 ns;
S(0) <= not S(0) after 20 ns;
   end process;
END;

Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.

It is intended only for educational purpose.