Sequence Detector (Mealy Machine-1011) VHDL Code

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A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output.

In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mealy_1011 is
    Port ( W, clk, reset : in  STD_LOGIC;
           z : out  STD_LOGIC);
end Mealy_1011;

architecture Behavioral of Mealy_1011 is
type state_type is (a,b,c,d);
signal Y : state_type;
begin
process(clk,reset)
begin
if(reset ='1') then
Y <= A;
ELSIF(RISING_EDGE(CLK)) THEN
CASE Y IS
WHEN A =>
IF(W='0') THEN
y <= A; z <= '0';
ELSE
Y <= B; z <= '0';
END IF;
WHEN B =>
IF(W='0') THEN
Y <= C; z <= '0';
ELSE
Y <= B; z <= '0';
END IF;
WHEN C =>
IF(W='0') THEN
Y <= A; z <= '0';
ELSE
Y <= D; z <= '0';
END IF;
WHEN D =>
IF(W='0') THEN
Y <= C; z <= '0';
ELSE
Y <= A; z <= '1';
END IF;
END CASE;
END IF;
END PROCESS;
end Behavioral;


Testbench:

  -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      w <= '1'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '0'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '0'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '0'; wait for clk_period;
w <= '1'; wait for clk_period;
w <= '1'; wait for clk_period;
   end process;

(Only Stimulus process is given here)

Output:


In the above waveform, till 5ns (i.e. till the first active edge, Output is 'Z') then in successive 4 clock cycles (i.e. at 15,25,35 and 45ns) circuit receives data 1011 respectively, thus producing Output Z'=1' at 45 ns which remains valid till next active edge. After this the circuit continues to detect the sequence.


Comments

  1. Srinatha6 January 2023 at 14:04

    All the codes are neatly written and are readable. Very nice Blog.

    ReplyDelete

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