Demultiplexer VHDL Code 1-to-4 (case-when)

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The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer.

In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using case-when statement.


VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demux_14 is
    Port ( Din : in  STD_LOGIC;
           Sel : in  STD_LOGIC_VECTOR (1 downto 0);
           dout : out  STD_LOGIC_VECTOR (3 downto 0));
end Demux_14;
architecture Behavioral of Demux_14 is
begin
process(din,sel)
begin
case sel is
when "11" => dout <= din&"000";
when "10" => dout <= '0'&din&"00";
when "01" => dout <= "00"&din&'0';
when others => dout <= "000"&din;
end case;
end process;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Demux_14_tb IS
END Demux_14_tb;
 
ARCHITECTURE behavior OF Demux_14_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Demux_14
    PORT(
         Din : IN  std_logic;
         Sel : IN  std_logic_vector(1 downto 0);
         dout : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal Din : std_logic := '0';
   signal Sel : std_logic_vector(1 downto 0) := (others => '0');

  --Outputs
   signal dout : std_logic_vector(3 downto 0);
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Demux_14 PORT MAP (
          Din => Din,
          Sel => Sel,
          dout => dout
        );

   -- Stimulus process
   stim_proc: process(din,sel)
   begin
din <= '1';
sel(1) <= not sel(1) after 40 ns;
sel(0) <= not sel(0) after 20 ns;
   end process;
END;


Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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