4-to-1 Multiplexer VHDL Code (when-else)

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4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using when-else statement (concurrent statement). Also enable signal is added for better control. If Enable='1',(i.e.active HIGH), the MUX will work else, with Enable='0', the MUX circuit will produce 'Z' as output.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux41 is
    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);
           S0,S1 : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Y : out  STD_LOGIC);
end Mux41;
architecture Behavioral of Mux41 is
begin
Y <= I(0) when En = '1' and S1='0' and s0='0' else
I(1) when En = '1' and S1='0' and s0='1' else
I(2) when En = '1' and S1='1' and s0='0' else
I(3) when En = '1' and S1='1' and s0='1' else
'Z';
end Behavioral;

Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Mux41_tb IS
END Mux41_tb;
 
ARCHITECTURE behavior OF Mux41_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Mux41
    PORT(
         I : IN  std_logic_vector(3 downto 0);
         S0 : IN  std_logic;
         S1 : IN  std_logic;
         En : IN  std_logic;
         Y : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal I : std_logic_vector(3 downto 0) := (others => '0');
   signal S0 : std_logic := '0';
   signal S1 : std_logic := '0';
   signal En : std_logic := '0';

  --Outputs
   signal Y : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Mux41 PORT MAP (
          I => I,
          S0 => S0,
          S1 => S1,
          En => En,
          Y => Y
        );

   -- Stimulus process
   stim_proc: process
   begin
En <= '1';
I <= "1010";
s1<='0'; s0<='0'; wait for 5 ns;
s1<='0'; s0<='1'; wait for 5 ns;
s1<='1'; s0<='0'; wait for 5 ns;
s1<='1'; s0<='1'; wait for 5 ns;
WAIT FOR 20 NS;
En <= '0';
I <= "1110";
s1<='0'; s0<='0'; wait for 5 ns;
s1<='0'; s0<='1'; wait for 5 ns;
s1<='1'; s0<='0'; wait for 5 ns;
s1<='1'; s0<='1'; wait for 5 ns;
wait for 15 ns;
   end process;
END;

Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

Comments

  1. Poonam4 December 2022 at 21:47

    Thank you. I was looking for same design with multiple statements and Your blog provided exactly what I needed.

    ReplyDelete

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