Left Shift Register VHDL Code

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Shift registers in digital systems are group of Flip-flops connected together to store multiple bits of data and are used to Shift the stored data to Left or Right. The register that shifts the bits towards left (from LSb to MSb) are called Left Shift Registers and the one which shifts the bits towards right (from MSb to LSb) are called Right Shift Registers.
The following VHDL code is written for 4-bit Left Shift Register which allows serial input and serial output (SISO). The design has asynchronous reset pin (rst), when active (HIGH), resets (output=0000) the Shift register. Otherwise, the design will load 1-bit data on every active edge of the clock into the register and at the same time 1-bit data output is generated.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Left_SR is
    Port ( Sin : in  STD_LOGIC;
           clk,rst : in  STD_LOGIC;
           Sout : out  STD_LOGIC);
end Left_SR;

architecture Behavioral of Left_SR is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst ='1') then
temp <= "0000";
elsif(clk'event and clk='1') then
for i in 0 to 2 loop
temp (i+1) <= temp(i);
end loop;
temp(0) <= sin;
end if;
end process;
sout <= temp(3);
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY SISO_Left_SR IS
END SISO_Left_SR;
 
ARCHITECTURE behavior OF SISO_Left_SR IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Left_SR
    PORT(
         Sin : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         Sout : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Sin : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal Sout : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Left_SR PORT MAP (
          Sin => Sin,
          clk => clk,
          rst => rst,
          Sout => Sout
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin
   rst<='1'; wait for 10 ns;
rst <='0'; sin<='1'; wait for 10 ns;
sin<='0'; wait for 80 ns;
   end process;
END;


Output:



The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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