1-bit Full Adder (Dataflow & Behavioral Style)

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The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry.

VHDL Code: (Dataflow)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_DF is
    Port ( A,B,Cin : in  STD_LOGIC;
           Sum,Carry : out  STD_LOGIC);
end FA_DF;
architecture Behavioral of FA_DF is
begin
Sum <= A xor B xor Cin;
 Carry <= (A and B) or (B and Cin) or (A and Cin);
end Behavioral;

VHDL Code: (Behavioral)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_DF is
    Port ( A,B,Cin : in  STD_LOGIC;
           Sum,Carry : out  STD_LOGIC);
end FA_DF;
architecture Behavioral of FA_DF is
begin
process(A,B,Cin)
 begin
 if(A='0' and B='0' and Cin='0') then
 Sum <= '0'; Carry <='0';
 elsif(A='0' and B='0' and Cin='1') then
 Sum <= '1'; Carry <='0';
 elsif(A='0' and B='1' and Cin='0') then
 Sum <= '1'; Carry <='0';
 elsif(A='0' and B='1' and Cin='1') then
 Sum <= '0'; Carry <='1';
 elsif(A='1' and B='0' and Cin='0') then
 Sum <= '1'; Carry <='0';
 elsif(A='1' and B='0' and Cin='1') then
 Sum <= '0'; Carry <='1';
 elsif(A='1' and B='1' and Cin='0') then
 Sum <= '1'; Carry <='1';
 elsif(A='1' and B='1' and Cin='1') then
 Sum <= '1'; Carry <='1';
 else
 Sum <= 'Z'; Carry <= 'Z';
 end if;
 end process;
end Behavioral;

Testbench:

The testbench is written in a different way, as the inputs are initialized to '0', the statements used will generate all possible input combinations for the circuit under test.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY FA_tb IS
END FA_tb;
 
ARCHITECTURE behavior OF FA_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FA_DF
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Cin : IN  std_logic;
         Sum : OUT  std_logic;
         Carry : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal Cin : std_logic := '0';

  --Outputs
   signal Sum : std_logic;
   signal Carry : std_logic;
   
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: FA_DF PORT MAP (
          A => A,
          B => B,
          Cin => Cin,
          Sum => Sum,
          Carry => Carry
        );
   -- Stimulus process
   stim_proc: process(A,B,Cin)
   begin
A <= not A after 40 ns;
B <= not B after 20 ns;
Cin <= not Cin after 10 ns;
   end process;

END;


Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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