Demultiplexer VDHL Code 1-to-8 (when-else)

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The following VHDL Code is written using when-else statement.
D input is permanently held logic HIGH, while select input S changes through 000 to 111, connecting D to output line Y0 to Y7 respectively.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Demux_1to8 is
    Port ( D : in  STD_LOGIC;
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           Y : out  STD_LOGIC_VECTOR (7 downto 0));
end Demux_1to8;

architecture Behavioral of Demux_1to8 is

begin

     Y <=  "0000000"&D  when S="000" else
"000000"&D&'0'     when S="001" else
"00000"&D&"00"   when S="010" else
"0000"&D&"000"   when S="011" else
"000"&D&"0000"   when S="100" else
"00"&D&"00000"   when S="101" else
'0'&D&"000000"     when S="110" else
D&"0000000"    when S="111" else
"ZZZZZZZZ";
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Demux_tb IS
END Demux_tb;
 
ARCHITECTURE behavior OF Demux_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Demux_1to8
    PORT(
         D : IN  std_logic;
         S : IN  std_logic_vector(2 downto 0);
         Y : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal D : std_logic := '0';
   signal S : std_logic_vector(2 downto 0) := (others => '0');

  --Outputs
   signal Y : std_logic_vector(7 downto 0);
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Demux_1to8 PORT MAP (
          D => D,
          S => S,
          Y => Y
        );

   -- Stimulus process
   stim_proc: process
   begin
     D<='1';
  S <= "000"; wait for 5 ns;
  S <= "001"; wait for 5 ns;
  S <= "010"; wait for 5 ns;
  S <= "011"; wait for 5 ns;
  S <= "100"; wait for 5 ns;
  S <= "101"; wait for 5 ns;
  S <= "110"; wait for 5 ns;
  S <= "111"; wait for 5 ns;
  S <= "UXZ"; wait for 5 ns; 
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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