Xilinx 14.7 Webpack New Project Wizard

-
This video will guide you through the Xilinx ISE 14.7 webpack (free) New Project Creation wizard. The video covers the 2 input AND gate design using dataflow style modelling and testing the same design by writing the testbench.


Subscribe the channel to get new video notifications.
Thank You.

Comments

  1. Adiganesh1 December 2022 at 16:43

    Nice video with simple example to understand.

    ReplyDelete

Post a Comment

Popular posts from this blog

3-to-8 line Decoder VHDL Code (with-select-when)

-
Image
A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^n unique outputs.  VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder38 is     Port ( A : in  STD_LOGIC_VECTOR(2 downto 0);            G1,G2b,G3b : in  STD_LOGIC;            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end decoder38; architecture Behavioral of decoder38 is signal en : std_logic_vector (5 downto 0) ; begin en <= (G1 & G2b & G3b) & A ; with en select  y <= "00000001" when "100000", "00000010" when "100001", "00000100" when "100010", "00001000" when "100011", "00010000" when "100100", "00100000" when "100101", "01000000" when "100110", "10000000" when "100111", "00000000" when others; en...
Read more

4-to-1 Multiplexer (if-else Statement)

-
Image
  The  4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  if-else  statement (sequential statement). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux41 is     Port ( i0,i1,i2,i3,s0,s1 : in  STD_LOGIC;            Y : out  STD_LOGIC); end Mux41; architecture Mux41 of Mux41 is begin process(i0,i1,i2,i3,s0,s1) begin if(s1='0' and s0='0') then Y <= i0; elsif(s1='0' and s0='1') then Y <= i1; elsif(s1='1' and s0='0') then Y <= i2; elsif(s1='1' and s0='1') then Y <= i3; else  Y <= 'Z'; end if; end process; end Mux41; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY mux41_tb IS END mux41_tb;   ARCHITECTURE behavior OF mux41_tb IS      COMPONENT Mux41     PORT(          i0 : IN  std_logic; ...
Read more

1-bit Full Adder (Dataflow & Behavioral Style)

-
Image
The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry. VHDL Code: (Dataflow) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin Sum <= A xor B xor Cin; Carry <= (A and B) or (B and Cin) or (A and Cin); end Behavioral; VHDL Code: (Behavioral) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0') then Sum <= '0'; Carry <='0'; elsif(A='0' and B='0' and Cin='1') then Sum <= '1'; Carry <='0'; elsif(A='0' and B='1' and Cin='0') then Su...
Read more