4-bit Comparator VHDL Code (when-else statement)

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Comparator circuit is used to compare two input signals and generates signals accordingly. The 4-bit comparator circuit compares two 4-bit numbers and generates 1-bit signals less than(Lt), greater than(Gt) or equal to(Eq). Irrespective of size of input numbers being compared the output signals remains the same.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity compare_4 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Eq : out  STD_LOGIC;
           Gt : out  STD_LOGIC;
           Lt : out  STD_LOGIC);
end compare_4;

architecture Behavioral of compare_4 is
begin
Eq <= '1' WHEN A = B ELSE '0' ;
Gt <= '1' WHEN A > B ELSE '0' ;
Lt <= '1' WHEN A < B ELSE '0' ;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Compare_4_tb IS
END Compare_4_tb;
 
ARCHITECTURE behavior OF Compare_4_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT compare_4
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         Eq : OUT  std_logic;
         Gt : OUT  std_logic;
         Lt : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs
   signal Eq : std_logic;
   signal Gt : std_logic;
   signal Lt : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: compare_4 PORT MAP (
          A => A,
          B => B,
          Eq => Eq,
          Gt => Gt,
          Lt => Lt
        );

   -- Stimulus process
   stim_proc: process
   begin
A <= "0101";
B <= "1100";
wait for 20 ns;
A <= "1101";
B <= "1100";
wait for 20 ns;
A <= "0101";
B <= "0101";
wait for 20 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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