Comparator VHDL Code (if-else statement)

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VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Compare_4 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Eq : out  STD_LOGIC;
           Gt : out  STD_LOGIC;
           Lt : out  STD_LOGIC);
end Compare_4;

architecture Behavioral of Compare_4 is

begin
process (a,b) is
    begin
        if (a=b) then
            eq <= '1';
            gt <= '0';
            lt <= '0';
        elsif (a<b) then
            eq <= '0';
            gt <= '0';
            lt <= '1';
        else
            eq <= '0';
            gt <= '1';
            lt <= '0';
        end if;
    end process;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY compare_4_tb IS
END compare_4_tb;
 
ARCHITECTURE behavior OF compare_4_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Compare_4
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         Eq : OUT  std_logic;
         Gt : OUT  std_logic;
         Lt : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs
   signal Eq : std_logic;
   signal Gt : std_logic;
   signal Lt : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: Compare_4 PORT MAP (
          A => A,
          B => B,
          Eq => Eq,
          Gt => Gt,
          Lt => Lt
        );

   -- Stimulus process
   stim_proc: process
   begin
A <= "1010";
B <= "0101";
wait for 20 ns;
A <= "1010";
B <= "1010";
wait for 20 ns;
A <= "1010";
B <= "1101";
wait for 20 ns;
   end process;
END;


Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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