4-to-1 Multiplexer VHDL Code (case-when)

The 4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using case-when statement (requential statement).

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41 is
    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_vector(1 downto 0);
           Y : out  STD_LOGIC);
end Mux_41;
architecture Behavioral of Mux_41 is
begin
process(I,s)
begin
case s is
when "00" => Y <= I(0);
when "01" => Y <= I(1);
when "10" => Y <= I(2);
when "11" => Y <= I(3);
when others => Y <= 'Z';
end case;
end process;
end Behavioral;

Testbench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

ENTITY Mux_41_tb IS

END Mux_41_tb;

 

ARCHITECTURE behavior OF Mux_41_tb IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT Mux_41

    PORT(

         I : IN  std_logic_vector(3 downto 0);

         s : IN  std_logic_vector(1 downto 0);

         Y : OUT  std_logic

        );

    END COMPONENT;

    

   --Inputs

   signal I : std_logic_vector(3 downto 0) := (others => '0');

   signal s : std_logic_vector(1 downto 0) := (others => '0');

  --Outputs

   signal Y : std_logic;

    

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

   uut: Mux_41 PORT MAP (

          I => I,

          s => s,

          Y => Y

        );

   -- Stimulus process

   stim_proc: process(I,S)

   begin

I <= "1010";  

s(1) <= not s(1) after 40 ns;

s(0) <= not s(0) after 20 ns;

   end process;

END;

Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.

It is intended only for educational purpose.