Half Adder (Behavioral Style)

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The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HA_behav is
    Port ( A,B : in  STD_LOGIC;
           Sum,Carry : out  STD_LOGIC);
end HA_behav;
architecture Behavioral of HA_behav is
begin
process(A,B)
 begin
 if(A='0' and B='0') then
 Sum <= '0'; Carry <= '0';
 elsif(A='1' and B='1') then
 Sum <= '0'; Carry <= '1';
 else
 Sum <= '1'; Carry <= '0';
 end if;
 end process;
end Behavioral;


Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY HA_behav_tb IS
END HA_behav_tb;
 
ARCHITECTURE behavior OF HA_behav_tb IS 

    COMPONENT HA_behav
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Sum : OUT  std_logic;
         Carry : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';

  --Outputs
   signal Sum : std_logic;
   signal Carry : std_logic;
  
BEGIN
   uut: HA_behav PORT MAP (
          A => A,
          B => B,
          Sum => Sum,
          Carry => Carry
        );

   stim_proc: process
   begin
      A <= '0'; B <= '0'; wait for 20 ns;
A <= '0'; B <= '1'; wait for 20 ns;
  A <= '1'; B <= '0'; wait for 20 ns;
   A <= '1'; B <= '1'; wait for 20 ns;
   end process;
END;


Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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