T Flip-flop VHDL Code

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If the T input is high, the T flip-flop changes state (i.e. toggles) whenever the clock input is applied. If the T input is low, the flip-flop holds the previous value.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FF is
    Port ( T : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           Q : out  STD_LOGIC;
           rst : in  STD_LOGIC);
end T_FF;

architecture Behavioral of T_FF is
signal temp : std_logic;
begin
process(clk,rst,t)
begin
if (rst='1') then
temp <= '0';
elsif(clk'event and clk ='1') then
if(T='1') then
temp <= not temp;
end if;
end if;
end process;
Q <= temp;
end Behavioral;



Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY T_FF_tb IS
END T_FF_tb;
 
ARCHITECTURE behavior OF T_FF_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT T_FF
    PORT(
         T : IN  std_logic;
         clk : IN  std_logic;
         Q : OUT  std_logic;
         rst : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal T : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal Q : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: T_FF PORT MAP (
          T => T,
          clk => clk,
          Q => Q,
          rst => rst
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin
      rst <= '1';
T <= '1';
wait for 30 ns;
rst <= '0';
T <= '0';
wait for 30 ns;
T <= '1';
wait for 60 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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