D Flip-flop VHDL Code

-
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store 1-bit of information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic.
The D flip-flop, which is widely used, also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge or falling edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change.


VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF is
    Port ( D : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end D_FF;

architecture Behavioral of D_FF is

begin
process
begin
--if (clk'event and clk='1') then
wait until clk'event and clk='1';    -- additionally comment this and keep if for clock
Q <= D;
--end if;
end process;
end Behavioral;



Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY D_FF_tb IS
END D_FF_tb;
 
ARCHITECTURE behavior OF D_FF_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT D_FF
    PORT(
         D : IN  std_logic;
         clk : IN  std_logic;
         Q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal D : std_logic := '0';
   signal clk : std_logic := '0';

  --Outputs
   signal Q : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: D_FF PORT MAP (
          D => D,
          clk => clk,
          Q => Q
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin
D <= '1';
wait for 44 ns;
D <= '0';
wait for 13 ns;
D <= '1';
wait for 27 ns;
D <= '0';
wait for 12 ns;
   end process;
END;


Output:

VHDL Code for D Flip-flop with asynchronous clear input:

D flip-flops can have asynchronous clear, which can be independent of the clock. Regardless of the clock, the clear can change the output Q to zero, which can cause asynchronous output.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_aclr is
    Port ( D : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end D_FF_aclr;

architecture Behavioral of D_FF_aclr is

begin
process(clk,clr,D)
begin
if (clr ='1') then
Q <= '0';
elsif (clk'event and clk ='1') then
Q <= D;
end if;
end process;
end Behavioral;


Testbench:

stim_proc: process
   begin
clr <= '1';
D <= '1';
wait for 14 ns;
clr <= '0';
D <= '0';
wait for 11 ns;
D<= '1';
clr <= '1' after 11 ns;
wait for 29 ns;
D <= '0';
wait for 13 ns;
   end process;

(Only Stimulus process is given here)


Output:


VHDL Code for D Flip-flop with synchronous clear input:

D flip-flop with synchronous clear means the output can reset to zero with the clear input but only with the clock, which makes the clear input dependent on the clock pulse; without clock pulse clear will not be able to set the output Q to zero, which will give you a synchronous output always.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_clr is
    Port ( D : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end D_FF_clr;

architecture Behavioral of D_FF_clr is

begin
process
begin
wait until clk'event and clk='1';
if (clr ='1') then
Q <= '0';
else
Q <= D;
end if;
end process;
end Behavioral;


Testbench:

-- Stimulus process
   stim_proc: process
   begin
D <= '1';
clr <= '1';
wait for 17 ns;
D <= '0';
clr <= '0';
wait for 12 ns;
D <= '1';
wait for 14 ns;
D <='0';
wait for 4 ns;
   end process;

(Only Stimulus process is given here)


Output: 



The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

Comments

Post a Comment

Popular posts from this blog

3-to-8 line Decoder VHDL Code (with-select-when)

-
Image
A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^n unique outputs.  VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder38 is     Port ( A : in  STD_LOGIC_VECTOR(2 downto 0);            G1,G2b,G3b : in  STD_LOGIC;            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end decoder38; architecture Behavioral of decoder38 is signal en : std_logic_vector (5 downto 0) ; begin en <= (G1 & G2b & G3b) & A ; with en select  y <= "00000001" when "100000", "00000010" when "100001", "00000100" when "100010", "00001000" when "100011", "00010000" when "100100", "00100000" when "100101", "01000000" when "100110", "10000000" when "100111", "00000000" when others; en
Read more

Sequence Detector (Mealy Machine-1011) VHDL Code

-
Image
A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output. In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mealy_1011 is     Port ( W, clk, reset : in  STD_LOGIC;            z : out  STD_LOGIC); end Mealy_1011; architecture Behavioral of Mealy_1011 is type state_type is (a,b,c,d); signal Y : state_type; begin process(clk,reset) begin if(reset ='1') then Y <= A; ELSIF(RISING_EDGE(CLK)) THEN CASE Y IS WHEN A => IF(W='0') THEN y <= A; z <= '0
Read more

8-TO-1 Multiplexer VHDL Code (Structural Style)

-
Image
In electronics Multiplexer (also called MUX) is a circuit that has several inputs and one output line. The output depends on the select line input signal. In the following example the 8-to-1 MUX is written in structural modelling style while the components which are used in design are written with behavioral style. (4-to-1 MUX is written using sequential statement case-when while 2-to-1 MUX is written using concurrent statement when-else .) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_81 is     Port ( D : in  STD_LOGIC_VECTOR (7 downto 0);            S : in  STD_LOGIC_VECTOR (2 downto 0);            Y : out  STD_LOGIC); end Mux_81; architecture Behavioral of Mux_81 is signal y1,y2 : std_logic; component Mux_41 is port(I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end component; component Mux_21 is port (I0,I1,S : in std_logic; Y : out std_logic); end component; begin M1 : Mux_41 port map (I(0)=>
Read more