VHDL Design

The following VHDL Code is written using when-else statement. D input is permanently held logic HIGH, while select input S changes through 000 to 111, connecting D to output line Y0 to Y7 respectively. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Demux_1to8 is     Port ( D : in  STD_LOGIC;            S : in  STD_LOGIC_VECTOR (2 downto 0);            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end Demux_1to8; architecture Behavioral of Demux_1to8 is begin      Y <=  "0000000"&D   when S="000" else "000000"&D&'0'      when S="001" else "00000"&D&"00"    when S="010" else "0000"&D&"000"   when S="011" else "000"&D&"0000"   when S="100" else "00"&D&"00000"   when S="101" else '0'&D&"000000"     when S="110

The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using case-when  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Demux_14 is     Port ( Din : in  STD_LOGIC;            Sel : in  STD_LOGIC_VECTOR (1 downto 0);            dout : out  STD_LOGIC_VECTOR (3 downto 0)); end Demux_14; architecture Behavioral of Demux_14 is begin process(din,sel) begin case sel is when "11" => dout <= din&"000"; when "10" => dout <= '0'&din&"00"; when "01" => dout <= "00"&din&'0'; when others => dout <= "000"&din; end case; end process; end Behavioral; Testbench: LIBRAR

This video will guide you through the Xilinx ISE 14.7 webpack (free) New Project Creation wizard. The video covers the 2 input AND gate design using dataflow style modelling and testing the same design by writing the testbench. Subscribe the channel to get new video notifications. Thank You.

Shift registers in digital systems are group of Flip-flops connected together to store multiple bits of data and are used to Shift the stored data to Left or Right.  The register that shifts the bits towards left (from LSb to MSb) are called Left Shift Registers and the one which shifts the bits towards right (from MSb to LSb) are called Right Shift Registers. The following VHDL code is written for 4-bit Left Shift Register which allows serial input and serial output (SISO). The design has asynchronous reset pin (rst), when active (HIGH), resets (output=0000) the Shift register. Otherwise, the design will load 1-bit data on every active edge of the clock into the register and at the same time 1-bit data output is generated. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Left_SR is     Port ( Sin : in  STD_LOGIC;            clk,rst : in  STD_LOGIC;            Sout : out  STD_LOGIC); end Left_SR; architecture Behavioral of Left_SR is signal temp : std_logic_vector(3 downt

The  4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  case-when  statement (requential statement). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_41 is     Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);            s : in  STD_LOGIC_vector(1 downto 0);            Y : out  STD_LOGIC); end Mux_41; architecture Behavioral of Mux_41 is begin process(I,s) begin case s is when "00" => Y <= I(0); when "01" => Y <= I(1); when "10" => Y <= I(2); when "11" => Y <= I(3); when others => Y <= 'Z'; end case; end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY Mux_41_tb IS END Mux_41_tb;   ARCHITECTURE behavior OF Mux_41_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT Mux_41     PORT(          I : IN  std_logic_vector(

4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  with-select-when  statement (concurrent statement). Also enable signal is added for better control. If Enable='1',(i.e.active HIGH), the MUX will work else, with Enable='0', the MUX circuit will produce 'Z' as output. The VHDL code starts with declaration of 3-bit signal 'sig', which gets the value from Enable signal 'en' and two select line input signals S1 and S0 respectively. (& is the concatenation operator) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_41 is     Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);            s0 : in  STD_LOGIC;            s1 : in  STD_LOGIC;            en : in  STD_LOGIC;            Y : out  STD_LOGIC); end Mux_41; architecture Behavioral of Mux_41 is signal sig : std_logic_vector(2 downto 0); begin sig <= En&s1&s0; with sig select Y <= I(0) when &

4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using when-else statement (concurrent statement). Also enable signal is added for better control. If Enable='1',(i.e.active HIGH), the MUX will work else, with Enable='0', the MUX circuit will produce 'Z' as output. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux41 is     Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);            S0,S1 : in  STD_LOGIC;            En : in  STD_LOGIC;            Y : out  STD_LOGIC); end Mux41; architecture Behavioral of Mux41 is begin Y <= I(0) when En = '1' and S1='0' and s0='0' else I(1) when En = '1' and S1='0' and s0='1' else I(2) when En = '1' and S1='1' and s0='0' else I(3) when En = '1' and S1='1' and s0='1' else 'Z'; end Behavioral; Testbench: LIBRARY ieee; USE ieee.s

In electronics Multiplexer (also called MUX) is a circuit that has several inputs and one output line. The output depends on the select line input signal. In the following example the 8-to-1 MUX is written in structural modelling style while the components which are used in design are written with behavioral style. (4-to-1 MUX is written using sequential statement case-when while 2-to-1 MUX is written using concurrent statement when-else .) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_81 is     Port ( D : in  STD_LOGIC_VECTOR (7 downto 0);            S : in  STD_LOGIC_VECTOR (2 downto 0);            Y : out  STD_LOGIC); end Mux_81; architecture Behavioral of Mux_81 is signal y1,y2 : std_logic; component Mux_41 is port(I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end component; component Mux_21 is port (I0,I1,S : in std_logic; Y : out std_logic); end component; begin M1 : Mux_41 port map (I(0)=>

1-bit Full subtractor circuit is used to subtract two 1-bit numbers along with borrow, if any, and generates outputs Difference and Borrow. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FS is     Port ( D_1 : in  STD_LOGIC;            D_2 : in  STD_LOGIC;            Bin : in  STD_LOGIC;            Bout : out  STD_LOGIC;            Dout : out  STD_LOGIC); end FS; architecture structural of FS is signal d1,b1,b2: std_logic; component HS is port(A,B : in std_logic; diff, borrow: out std_logic); end component; begin HS1 : HS port map(A =>D_1,B=>D_2,diff=>d1,borrow=>b1); HS2 : HS port map(A =>d1,B=>Bin,diff=>Dout,borrow=>b2); Bout <= b1 or b2; end structural; VHDL Code for component: Component Half subtractor is written in behavioral style modelling. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS is     Port ( A : in  STD_LOGIC;            B : in  STD_LOGIC;            Diff : out  STD_LOGIC;            Borrow : out  STD_LOG

4-bit Full Adder circuit is used to add two 4-bit numbers along with Carry,if any, and generates 4-bit output Sum and 1-bit Carry out. In the following VHDL example, for testing, only four input conditions (four 4-bit Numbers ) are considered. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_4 is     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);            B : in  STD_LOGIC_VECTOR (3 downto 0);            Cin : in  STD_LOGIC;            Sout : out  STD_LOGIC_VECTOR (3 downto 0);            Cout : out  STD_LOGIC); end FA_4; architecture Behavioral of FA_4 is component FA is port(A,B,Cin : in  STD_LOGIC; S,C : out  STD_LOGIC); end component; signal c1,c2,c3 : STD_LOGIC; begin FA1: fa port map(A(0),B(0),Cin,Sout(0),c1); FA2: fa port map(A(1),B(1),C1,Sout(1),c2); FA3: fa port map(A(2),B(2),C2,Sout(2),c3); FA4: fa port map(A(3),B(3),C3,Sout(3),Cout); end Behavioral; VHDL Code for Component: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA is     Port ( A,B

The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry. The below code is written in mixed style modelling that uses both, Structural and Dataflow style. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FullAdder is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FullAdder; architecture mixed_style of FullAdder is component halfadder is port(A,B: in STD_LOGIC; S,C: out STD_LOGIC); end component; signal S1,C1,C2: STD_LOGIC;   -- used for connecting the module signals internally. begin HA1: halfadder port map(A,B,s1,c1); HA2: halfadder port map(s1,Cin,Sum,c2); Carry <= c1 or c2; end mixed_style; VHDL code component halfadder : library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity halfadder is     Port ( A,B : in  STD_LOGIC;            S,C : out  STD_LOGIC); end halfadder; architecture Behavioral of halfadder is begin S <= A xor B; C <

The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation. The VHDL code for Half Adder circuit is written with structural modelling by using  andgate  and  xorgate  as components.   VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity halfadder is     Port ( A : in  STD_LOGIC;            B : in  STD_LOGIC;            Sum : out  STD_LOGIC;            Carry : out  STD_LOGIC); end halfadder; architecture structural of halfadder is component andgate is port(a,b: in std_logic; y: out std_logic); end component; component xorgate is port(a,b: in std_logic; y: out std_logic); end component; begin G1: andgate port map(A,B,Carry); G2: xorgate port map(A,B,Sum); end structural; VHDL Code for andgate is used from previous post. VHDL code for xorgate is written using Dataflow style modelling. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xorgate is     Port ( a,b : in 

VHDLCode: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity andgate is     Port ( A : in  STD_LOGIC;            B : in  STD_LOGIC;            Y : out  STD_LOGIC); end andgate; architecture Behavioral of andgate is begin process(A,B) begin if(A='1' and B='1') then Y <= '1'; else Y <= '0'; end if; end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY andgate_tb IS END andgate_tb;   ARCHITECTURE behavior OF andgate_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT andgate     PORT(          A : IN  std_logic;          B : IN  std_logic;          Y : OUT  std_logic         );     END COMPONENT;    --Inputs    signal A : std_logic := '0';    signal B : std_logic := '0';   --Outputs    signal Y : std_logic;     BEGIN   -- Instantiate the Unit Under Test (UUT)    uut: andgate PORT MAP (           A => A,           B => B,