VHDL AND gate (Behavioral)

VHDLCode:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity andgate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Y : out  STD_LOGIC);
end andgate;

architecture Behavioral of andgate is
begin
process(A,B)
begin
if(A='1' and B='1') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;

Testbench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

ENTITY andgate_tb IS

END andgate_tb;

 

ARCHITECTURE behavior OF andgate_tb IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT andgate

    PORT(

         A : IN  std_logic;

         B : IN  std_logic;

         Y : OUT  std_logic

        );

    END COMPONENT;

   --Inputs

   signal A : std_logic := '0';

   signal B : std_logic := '0';

  --Outputs

   signal Y : std_logic;

   

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

   uut: andgate PORT MAP (

          A => A,

          B => B,

          Y => Y

        );

   -- Stimulus process

   stim_proc: process

   begin

A<='0'; B<='0';

wait for 10 ns;

A<='0'; B<='1';

wait for 10 ns;

A<='1'; B<='0';

wait for 10 ns;

A<='1'; B<='1';

wait for 10 ns;

   end process;

END;

Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.

It is intended only for educational purpose.