VHDL AND gate (Behavioral)

-
VHDLCode:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity andgate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Y : out  STD_LOGIC);
end andgate;

architecture Behavioral of andgate is
begin
process(A,B)
begin
if(A='1' and B='1') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY andgate_tb IS
END andgate_tb;
 
ARCHITECTURE behavior OF andgate_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT andgate
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Y : OUT  std_logic
        );
    END COMPONENT;
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';

  --Outputs
   signal Y : std_logic;
   
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: andgate PORT MAP (
          A => A,
          B => B,
          Y => Y
        );

   -- Stimulus process
   stim_proc: process
   begin
A<='0'; B<='0';
wait for 10 ns;
A<='0'; B<='1';
wait for 10 ns;
A<='1'; B<='0';
wait for 10 ns;
A<='1'; B<='1';
wait for 10 ns;
   end process;
END;


Output:



The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

Comments

Post a Comment

Popular posts from this blog

3-to-8 line Decoder VHDL Code (with-select-when)

-
Image
A binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^n unique outputs.  VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder38 is     Port ( A : in  STD_LOGIC_VECTOR(2 downto 0);            G1,G2b,G3b : in  STD_LOGIC;            Y : out  STD_LOGIC_VECTOR (7 downto 0)); end decoder38; architecture Behavioral of decoder38 is signal en : std_logic_vector (5 downto 0) ; begin en <= (G1 & G2b & G3b) & A ; with en select  y <= "00000001" when "100000", "00000010" when "100001", "00000100" when "100010", "00001000" when "100011", "00010000" when "100100", "00100000" when "100101", "01000000" when "100110", "10000000" when "100111", "00000000" when others; en
Read more

8-TO-1 Multiplexer VHDL Code (Structural Style)

-
Image
In electronics Multiplexer (also called MUX) is a circuit that has several inputs and one output line. The output depends on the select line input signal. In the following example the 8-to-1 MUX is written in structural modelling style while the components which are used in design are written with behavioral style. (4-to-1 MUX is written using sequential statement case-when while 2-to-1 MUX is written using concurrent statement when-else .) VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux_81 is     Port ( D : in  STD_LOGIC_VECTOR (7 downto 0);            S : in  STD_LOGIC_VECTOR (2 downto 0);            Y : out  STD_LOGIC); end Mux_81; architecture Behavioral of Mux_81 is signal y1,y2 : std_logic; component Mux_41 is port(I : in std_logic_vector(3 downto 0); S : in std_logic_vector(1 downto 0); Y : out std_logic); end component; component Mux_21 is port (I0,I1,S : in std_logic; Y : out std_logic); end component; begin M1 : Mux_41 port map (I(0)=>
Read more

Sequence Detector (Mealy Machine-1011) VHDL Code

-
Image
A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output. In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mealy_1011 is     Port ( W, clk, reset : in  STD_LOGIC;            z : out  STD_LOGIC); end Mealy_1011; architecture Behavioral of Mealy_1011 is type state_type is (a,b,c,d); signal Y : state_type; begin process(clk,reset) begin if(reset ='1') then Y <= A; ELSIF(RISING_EDGE(CLK)) THEN CASE Y IS WHEN A => IF(W='0') THEN y <= A; z <= '0
Read more