Full Adder VHDL (Mixed Modelling)

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The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry.

The below code is written in mixed style modelling that uses both, Structural and Dataflow style.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
    Port ( A,B,Cin : in  STD_LOGIC;
           Sum,Carry : out  STD_LOGIC);
end FullAdder;
architecture mixed_style of FullAdder is
component halfadder is
port(A,B: in STD_LOGIC;
S,C: out STD_LOGIC);
end component;

 signal S1,C1,C2: STD_LOGIC;   -- used for connecting the module signals internally.
begin
HA1: halfadder port map(A,B,s1,c1);
HA2: halfadder port map(s1,Cin,Sum,c2);
Carry <= c1 or c2;
end mixed_style;

VHDL code component halfadder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
    Port ( A,B : in  STD_LOGIC;
           S,C : out  STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
S <= A xor B;
C <= A and B;
end Behavioral;

Testbench:

The testbench is written in a different way, as the inputs are initialized to '0', the statements used will generate all possible input combinations for the circuit under test.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY fulladder_tb IS
END fulladder_tb;
 
ARCHITECTURE behavior OF fulladder_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FullAdder
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Cin : IN  std_logic;
         Sum : OUT  std_logic;
         Carry : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal Cin : std_logic := '0';
  --Outputs
   signal Sum : std_logic;
   signal Carry : std_logic;
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: FullAdder PORT MAP (
          A => A,
          B => B,
          Cin => Cin,
          Sum => Sum,
          Carry => Carry
        );
   -- Stimulus process
   stim_proc: process(a,b,cin)
begin
A <= not a after 40 ns;
b <= not b after 20 ns;
Cin <= not Cin after 10 ns;
   end process;
END;


Output:





The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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