4-to-1 Multiplexer VHDL Code (with-select-when)

4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using with-select-when statement (concurrent statement). Also enable signal is added for better control. If Enable='1',(i.e.active HIGH), the MUX will work else, with Enable='0', the MUX circuit will produce 'Z' as output.
The VHDL code starts with declaration of 3-bit signal 'sig', which gets the value from Enable signal 'en' and two select line input signals S1 and S0 respectively. (& is the concatenation operator)

VHDL Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Mux_41 is

    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

           s0 : in  STD_LOGIC;

           s1 : in  STD_LOGIC;

           en : in  STD_LOGIC;

           Y : out  STD_LOGIC);

end Mux_41;

architecture Behavioral of Mux_41 is

signal sig : std_logic_vector(2 downto 0);

begin

sig <= En&s1&s0;

with sig select

Y <= I(0) when "100",

I(1) when "101",

I(2) when "110",

I(3) when "111",

'Z' when others;

end Behavioral;

Testbench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Mux_41_tb IS

END Mux_41_tb;

 

ARCHITECTURE behavior OF Mux_41_tb IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT Mux_41

    PORT(

         I : IN  std_logic_vector(3 downto 0);

         s0 : IN  std_logic;

         s1 : IN  std_logic;

         en : IN  std_logic;

         Y : OUT  std_logic

        );

    END COMPONENT;

    

   --Inputs

   signal I : std_logic_vector(3 downto 0) := (others => '0');

   signal s0 : std_logic := '0';

   signal s1 : std_logic := '0';

   signal en : std_logic := '0';

  --Outputs

   signal Y : std_logic;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: Mux_41 PORT MAP (

          I => I,

          s0 => s0,

          s1 => s1,

          en => en,

          Y => Y

        );

   -- Stimulus process

   stim_proc: process(I,en,s0,s1)

   begin

En <= '1';

I <= "1010";

s1 <= not s1 after 40 ns;

s0 <= not s0 after 20 ns;

   end process;

END;

Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.

It is intended only for educational purpose.