Full Subtractor

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1-bit Full subtractor circuit is used to subtract two 1-bit numbers along with borrow, if any, and generates outputs Difference and Borrow.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FS is
    Port ( D_1 : in  STD_LOGIC;
           D_2 : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           Bout : out  STD_LOGIC;
           Dout : out  STD_LOGIC);
end FS;
architecture structural of FS is
signal d1,b1,b2: std_logic;
component HS is
port(A,B : in std_logic;
diff, borrow: out std_logic);
end component;
begin
HS1 : HS port map(A =>D_1,B=>D_2,diff=>d1,borrow=>b1);
HS2 : HS port map(A =>d1,B=>Bin,diff=>Dout,borrow=>b2);
Bout <= b1 or b2;
end structural;

VHDL Code for component:

Component Half subtractor is written in behavioral style modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HS is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Diff : out  STD_LOGIC;
           Borrow : out  STD_LOGIC);
end HS;
architecture Behavioral of HS is
begin
process(A,B)
begin
if(a='0' and b='1') then
Diff <= '1'; Borrow <= '1';
elsif (a='1' and b='0') then 
Diff <= '1'; Borrow <= '0';
else
Diff <= '0'; Borrow <= '0';
end if;
end process;
end Behavioral;

Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
  
ENTITY FS_tb IS
END FS_tb;
 
ARCHITECTURE behavior OF FS_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FS
    PORT(
         D_1 : IN  std_logic;
         D_2 : IN  std_logic;
         Bin : IN  std_logic;
         Bout : OUT  std_logic;
         Dout : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal D_1 : std_logic := '0';
   signal D_2 : std_logic := '0';
   signal Bin : std_logic := '0';
  --Outputs
   signal Bout : std_logic;
   signal Dout : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: FS PORT MAP (
          D_1 => D_1,
          D_2 => D_2,
          Bin => Bin,
          Bout => Bout,
          Dout => Dout
        );

   -- Stimulus process
   stim_proc: process(D_1,D_2,Bin)
   begin
      -- hold reset state for 100 ns.
     D_1 <= not D_1 after 80 ns;
D_2 <= not D_2 after 40 ns;
Bin <= not Bin after 20 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.


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