Demultiplexer VDHL Code 1-to-8 (when-else)
The following VHDL Code is written using when-else statement. D input is permanently held logic HIGH, while select input S changes through 000 to 111, connecting D to output line Y0 to Y7 respectively. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Demux_1to8 is Port ( D : in STD_LOGIC; S : in STD_LOGIC_VECTOR (2 downto 0); Y : out STD_LOGIC_VECTOR (7 downto 0)); end Demux_1to8; architecture Behavioral of Demux_1to8 is begin Y <= "0000000"&D when S="000" else "000000"&D&'0' when S="001" else "00000"&D&"00" when S="010" else "0000"&D&"000" when S="011" else "000"&D&"0000" when S="100" else "00"&D&"00000" when S="101" else '0'&D&"000000" when S="110