VHDL Design

1-bit Full subtractor subtracts two 1-bit numbers along with previous borrow, if any. In the following design A and B are the Two input numbers with C as borrow. The VHDL Code uses Structural Modeling with Basic Gates as components. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FS is     Port ( A,B,C : in  STD_LOGIC;            Diff,Borr : out  STD_LOGIC); end FS; architecture Behavioral of FS is component andgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component orgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component xorgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component notgate is port(A : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; signal X1,n1,a1,a2,a3,o1 : STD_LOGIC; begin      g1:xorgate port map(A,B,x1);      g2:xorgate port map(x1,c,Diff);    ...

The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA_behav is     Port ( A,B : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end HA_behav; architecture Behavioral of HA_behav is begin process(A,B) begin if(A='0' and B='0') then Sum <= '0'; Carry <= '0'; elsif(A='1' and B='1') then Sum <= '0'; Carry <= '1'; else Sum <= '1'; Carry <= '0'; end if; end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY HA_behav_tb IS END HA_behav_tb;   ARCHITECTURE behavior OF HA_behav_tb IS      COMPONENT HA_behav     PORT(          A : IN  std_logic;          B : IN  std_logic;         ...

 Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_Struct is     Port ( A,B : in  STD_LOGIC;            Diff, Borr : out  STD_LOGIC); end HS_Struct; architecture Behavioral of HS_Struct is component andgate is port(A,B : IN STD_LOGIC; Y: OUT STD_LOGIC); end component; component xorgate is port(A,B : IN STD_LOGIC; Y: OUT STD_LOGIC); end component; signal invA : STD_LOGIC; begin invA <= (not A); G1: xorgate port map(A=>A,B=>B,Y=>Diff); G2: andgate port map(invA,B,Borr); end Behavioral; VHDL Code for components: AND Gate VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xorgate is     Port ( A,B : in  STD_LOGIC; ...

Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_Behav is     Port ( A,B : in  STD_LOGIC;            Diff, Borr : out  STD_LOGIC); end HS_Behav; architecture Behavioral of HS_Behav is begin process(A,B) begin if(A='0' and B='0') then Diff <='0'; Borr <='0'; elsif(A='0' and B='1') then Diff <='1'; Borr <='1'; -- Diff=A-B; Borr=A-B elsif(A='1' and B='0') then Diff <='1'; Borr <='0'; elsif(A='1' and B='1') then Diff <='0'; Borr <='0'; else Diff<='Z'; Borr<='Z'; end if; end process; end Behavi...

Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_DF is     Port ( A,B : in  STD_LOGIC;            Diff,Borr : out  STD_LOGIC); end HS_DF; architecture Behavioral of HS_DF is begin Diff <= A xor B; Borr <= (not A) and B; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY HS_tb IS END HS_tb;   ARCHITECTURE behavior OF HS_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT HS_DF     PORT(          A : IN  std_logic;          B : IN  std_logic;          Diff : OUT...

The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA_DF is     Port ( A,B : in  STD_LOGIC;            Sum, Carry : out  STD_LOGIC); end HA_DF; architecture Dataflow of HA_DF is begin Sum <= A xor B; Carry <= A and B; end Dataflow; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY HA_tb IS END HA_tb;   ARCHITECTURE behavior OF HA_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT HA_DF     PORT(          A : IN  std_logic;          B : IN  std_logic;          Sum : OUT  std_logic;          Carry : OUT  std_logic         );   ...

The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using with-select-when  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux is     Port ( Din : in  STD_LOGIC;            Dout : out  STD_LOGIC_VECTOR (3 downto 0);            Sel : in  STD_LOGIC_VECTOR (1 downto 0)); end demux; architecture Behavioral of demux is begin with sel select Dout <= "000"&Din when "00", "00"&Din&'0' when "01", '0'&Din&"00" when "10", Din&"000" when "11", "XXXX" when others; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY Demux_tb IS END Demux_tb; ...

  The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using  if-else  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux14 is     Port ( Din : in  STD_LOGIC;            Sel : in  STD_LOGIC_VECTOR (1 downto 0);            dout : out  STD_LOGIC_VECTOR (3 downto 0)); end demux14; architecture Behavioral of demux14 is begin process(din,sel) begin if(sel="00") then dout <= "000"&din; elsif(sel="01") then dout <= "00"&din&'0'; elsif(sel="10") then dout <= '0'&din&"00"; else dout <= din&"000"; end if; end process; end Behavioral; Testbenc...

  The  4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  if-else  statement (sequential statement). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux41 is     Port ( i0,i1,i2,i3,s0,s1 : in  STD_LOGIC;            Y : out  STD_LOGIC); end Mux41; architecture Mux41 of Mux41 is begin process(i0,i1,i2,i3,s0,s1) begin if(s1='0' and s0='0') then Y <= i0; elsif(s1='0' and s0='1') then Y <= i1; elsif(s1='1' and s0='0') then Y <= i2; elsif(s1='1' and s0='1') then Y <= i3; else  Y <= 'Z'; end if; end process; end Mux41; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY mux41_tb IS END mux41_tb;   ARCHITECTURE behavior OF mux41_tb IS      COMPONENT Mux41     PORT(          i0 : IN  std_logic; ...

The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry. VHDL Code: (Dataflow) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin Sum <= A xor B xor Cin; Carry <= (A and B) or (B and Cin) or (A and Cin); end Behavioral; VHDL Code: (Behavioral) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0') then Sum <= '0'; Carry <='0'; elsif(A='0' and B='0' and Cin='1') then Sum <= '1'; Carry <='0'; elsif(A='0' and B='1' and Cin='0') then Su...

A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output. In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mealy_1011 is     Port ( W, clk, reset : in  STD_LOGIC;            z : out  STD_LOGIC); end Mealy_1011; architecture Behavioral of Mealy_1011 is type state_type is (a,b,c,d); signal Y : state_type; begin process(clk,reset) begin if(reset ='1') then Y <= A; ELSIF(RISING_EDGE(CLK)) THEN CASE Y IS WHEN A => IF(W='0') THEN y <= A; z ...

In PISO type shift register, the data is given as input to all the flip-flops at the same time (simultaneously), and the circuit will produce the serial output. In the VHDL Code Pin: Parallel Input CLR: clear input (or RESET input) CLK: clock input L_S: Load/Shift signal, used to control whether to load the Shift register with new data on Pin (i.e. L_S='1')  or to shift the existing data in the Shift register (i.e. L_S='0'). Sout: Output Signal VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Left_SR is     Port ( Pin : in  STD_LOGIC_VECTOR (7 downto 0);            clr, clk, L_S : in  STD_LOGIC;            sout : out  STD_LOGIC); end Left_SR; architecture Behavioral of Left_SR is signal temp: std_logic_vector(7 downto 0); begin process(clk,clr) begin if(clr='1') then temp <= "00000000"; elsif (clk'event and clk='1') then if(L_S='1') then temp <=...

In digital design, a counter is a device which stores the number of times a particular event has occurred, often with respect to a clock signal. The most common type is a sequential digital logic circuit with an input line called the clock and multiple output lines representing the count. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity U_DCOUNTER is     Port ( RESET : in  STD_LOGIC;            U_D : in  STD_LOGIC;            CLK : in  STD_LOGIC;            Cout : out  STD_LOGIC_VECTOR (3 downto 0)); end U_DCOUNTER; architecture U_DCOUNTER of U_DCOUNTER is begin process(CLK,RESET) variable temp:STD_LOGIC_VECTOR (3 downto 0):="0000"; begin...

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