Half Subtractor (Dataflow Style Modelling)

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Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow.
The operation can be (A-B) or (B-A). The results will differ for these two operations.
The following VHDL code is written for (A-B).

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HS_DF is
    Port ( A,B : in  STD_LOGIC;
           Diff,Borr : out  STD_LOGIC);
end HS_DF;
architecture Behavioral of HS_DF is
begin
Diff <= A xor B;
 Borr <= (not A) and B;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY HS_tb IS
END HS_tb;
 
ARCHITECTURE behavior OF HS_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT HS_DF
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Diff : OUT  std_logic;
         Borr : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
  --Outputs
   signal Diff : std_logic;
   signal Borr : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: HS_DF PORT MAP (
          A => A,
          B => B,
          Diff => Diff,
          Borr => Borr
        );
   -- Stimulus process
   stim_proc: process(a,B)
   begin
        A <= not a after 40 ns;
B <= not B after 20 ns;
   end process;
END;

Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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