Half Subtractor (Behavioral Style Modelling)

Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow.

The operation can be (A-B) or (B-A). The results will differ for these two operations.

The following VHDL code is written for (A-B).

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HS_Behav is
    Port ( A,B : in  STD_LOGIC;
           Diff, Borr : out  STD_LOGIC);
end HS_Behav;

architecture Behavioral of HS_Behav is
begin
process(A,B)
begin
if(A='0' and B='0') then
Diff <='0'; Borr <='0';
elsif(A='0' and B='1') then
Diff <='1'; Borr <='1'; -- Diff=A-B; Borr=A-B
elsif(A='1' and B='0') then
Diff <='1'; Borr <='0';
elsif(A='1' and B='1') then
Diff <='0'; Borr <='0';
else
Diff<='Z'; Borr<='Z';
end if;
end process;
end Behavioral;

Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY HS_tb IS
END HS_tb;
 
ARCHITECTURE behavior OF HS_tb IS 
     -- Component Declaration for the Unit Under Test (UUT)
     COMPONENT HS_Behav
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Diff : OUT  std_logic;
         Borr : OUT  std_logic
        );
    END COMPONENT; 
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
  --Outputs
   signal Diff : std_logic;
   signal Borr : std_logic;
   
BEGIN
  -- Instantiate the Unit Under Test (UUT)
   uut: HS_Behav PORT MAP (
          A => A,
          B => B,
          Diff => Diff,
          Borr => Borr
        );
   -- Stimulus process
   stim_proc: process(A,B)
   begin
          A <= not A after 40 ns;
  B <= not B after 20 ns;
   end process;
END;

Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.

It is intended only for educational purpose.