Half Adder VHDL (Dataflow style modelling)

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The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation.

The VHDL code for Half Adder circuit is written with structural modelling by using andgate and xorgate as components. 

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HA_DF is
    Port ( A,B : in  STD_LOGIC;
           Sum, Carry : out  STD_LOGIC);
end HA_DF;
architecture Dataflow of HA_DF is
begin
Sum <= A xor B;
 Carry <= A and B;
end Dataflow;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY HA_tb IS
END HA_tb;
 
ARCHITECTURE behavior OF HA_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT HA_DF
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Sum : OUT  std_logic;
         Carry : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
  --Outputs
   signal Sum : std_logic;
   signal Carry : std_logic;
 
BEGIN
 
 -- Instantiate the Unit Under Test (UUT)
   uut: HA_DF PORT MAP (
          A => A,
          B => B,
          Sum => Sum,
          Carry => Carry
        );
 
   -- Stimulus process
   stim_proc: process
   begin
      A <= '0'; B <= '0'; wait for 20 ns;
 A <= '0'; B <= '1'; wait for 20 ns;
   A <= '1'; B <= '0'; wait for 20 ns;
    A <= '1'; B <= '1'; wait for 20 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.


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