1-Bit Full Subtractor (Structural Modeling)

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1-bit Full subtractor subtracts two 1-bit numbers along with previous borrow, if any.
In the following design A and B are the Two input numbers with C as borrow.

The VHDL Code uses Structural Modeling with Basic Gates as components.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FS is
    Port ( A,B,C : in  STD_LOGIC;
           Diff,Borr : out  STD_LOGIC);
end FS;

architecture Behavioral of FS is
component andgate is
port(A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
end component;
component orgate is
port(A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
end component;
component xorgate is
port(A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
end component;
component notgate is
port(A : IN STD_LOGIC;
Y : OUT STD_LOGIC);
end component;
signal X1,n1,a1,a2,a3,o1 : STD_LOGIC;
begin
    g1:xorgate port map(A,B,x1);
    g2:xorgate port map(x1,c,Diff);
    g3:notgate port map(a,n1);
    g4:andgate port map(n1,b,a1);
    g5:andgate port map(n1,c,a2);
    g6:andgate port map(b,c,a3);
    g7:orgate port map(a1,a2,o1);
    g8:orgate port map(o1,a3,Borr);
end Behavioral;


Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY FS_tb IS
END FS_tb;
 
ARCHITECTURE behavior OF FS_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FS
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
         Diff : OUT  std_logic;
         Borr : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C : std_logic := '0';

  --Outputs
   signal Diff : std_logic;
   signal Borr : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
  
BEGIN
  -- Instantiate the Unit Under Test (UUT)
   uut: FS PORT MAP (
          A => A,
          B => B,
          C => C,
          Diff => Diff,
          Borr => Borr
        );

   -- Stimulus process
   stim_proc: process(a,b,c)
   begin
     A <= not a after 40 ns;
  B <= not b after 20 ns;
  C <= not c after 10 ns;
   end process;
END;

Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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