1-to-4 Demultiplexer (Using with-select-when Statement)

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The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer.

In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using with-select-when statement.


VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demux is
    Port ( Din : in  STD_LOGIC;
           Dout : out  STD_LOGIC_VECTOR (3 downto 0);
           Sel : in  STD_LOGIC_VECTOR (1 downto 0));
end demux;

architecture Behavioral of demux is

begin
with sel select
Dout <= "000"&Din when "00",
"00"&Din&'0' when "01",
'0'&Din&"00" when "10",
Din&"000" when "11",
"XXXX" when others;
end Behavioral;


Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Demux_tb IS
END Demux_tb;
 
ARCHITECTURE behavior OF Demux_tb IS 
     -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT demux
    PORT(
         Din : IN  std_logic;
         Dout : OUT  std_logic_vector(3 downto 0);
         Sel : IN  std_logic_vector(1 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal Din : std_logic := '0';
   signal Sel : std_logic_vector(1 downto 0) := (others => '0');

  --Outputs
   signal Dout : std_logic_vector(3 downto 0);
 
BEGIN
  -- Instantiate the Unit Under Test (UUT)
   uut: demux PORT MAP (
          Din => Din,
          Dout => Dout,
          Sel => Sel
        );
   -- Stimulus process
   stim_proc: process
   begin
     Din <= '1';
  sel <= "00"; wait for 10 ns;
  sel <= "01"; wait for 10 ns;
  sel <= "10"; wait for 10 ns;
  sel <= "11"; wait for 10 ns;
   end process;
END;


Output:


The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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