VHDL Design

In digital design, a counter is a device which stores the number of times a particular event has occurred, often with respect to a clock signal. The most common type is a sequential digital logic circuit with an input line called the clock and multiple output lines representing the count. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity U_DCOUNTER is     Port ( RESET : in  STD_LOGIC;            U_D : in  STD_LOGIC;            CLK : in  STD_LOGIC;            Cout : out  STD_LOGIC_VECTOR (3 downto 0)); end U_DCOUNTER; architecture U_DCOUNTER of U_DCOUNTER is begin process(CLK,RESET) variable temp:STD_LOGIC_VECTOR (3 downto 0):="0000"; begin if (RESET='1')then temp:="0000"; elsif(CLK'event and CLK='1'

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If the T input is high, the T flip-flop changes state (i.e. toggles) whenever the clock input is applied. If the T input is low, the flip-flop holds the previous value. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity T_FF is     Port ( T : in  STD_LOGIC;            clk : in  STD_LOGIC;            Q : out  STD_LOGIC;            rst : in  STD_LOGIC); end T_FF; architecture Behavioral of T_FF is signal temp : std_logic; begin process(clk,rst,t) begin if (rst='1') then temp <= '0'; elsif(clk'event and clk ='1') then if(T='1') then temp <= not temp; end if; end if; end process; Q <= temp; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY T_FF_tb IS END T_FF_tb;   ARCHITECTURE behavior OF T_FF_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT T_FF     PORT(          T : IN  std_logic;          clk : IN  std_logic;          Q : OU

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store 1-bit of information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. The D flip-flop, which is widely used, also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge or falling edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FF is     Port ( D : in  STD_LOGIC;            clk : in  STD_LOGIC;            Q : out  STD_LOGIC); end D_FF; architecture Behavioral of D_FF is begin process begin --if (clk'event and clk='1') then wait until clk'event and clk='1';     -- additionally comm

The output of a priority encoder is the binary representation of the index of the most significant activated line, starting from zero. They are often used to control interrupt requests by acting on the highest priority interrupt input. If two or more inputs are given at the same time, the input having the highest priority will take precedence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Priority_encode is port(I : in std_logic_vector(3 downto 0); Y : out std_logic_vector(1 downto 0); P : out std_logic); end Priority_encode; architecture Behavioral of Priority_encode is begin P <= I(0) or I(1) or I(2) or I(3); Y <= "11" when I(3) = '1' else "10" when I(2) = '1' else "01" when I(1) = '1' else "00" when I(0) = '1' else "ZZ"; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY PE_tb IS END PE_tb;   ARCHITECTURE behavior OF PE_tb I

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Compare_4 is     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);            B : in  STD_LOGIC_VECTOR (3 downto 0);            Eq : out  STD_LOGIC;            Gt : out  STD_LOGIC;            Lt : out  STD_LOGIC); end Compare_4; architecture Behavioral of Compare_4 is begin process (a,b) is     begin         if (a=b) then             eq <= '1';             gt <= '0';             lt <= '0';         elsif (a<b) then             eq <= '0';             gt <= '0';             lt <= '1';         else             eq <= '0';             gt <= '1';             lt <= '0';         end if;     end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY compare_4_tb IS END compare_4_tb;   ARCHITECTURE behavior OF compare_4_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT Compa

Comparator circuit is used to compare two input signals and generates signals accordingly. The 4-bit comparator circuit compares two 4-bit numbers and generates 1-bit signals less than(Lt), greater than(Gt) or equal to(Eq). Irrespective of size of input numbers being compared the output signals remains the same. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity compare_4 is     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);            B : in  STD_LOGIC_VECTOR (3 downto 0);            Eq : out  STD_LOGIC;            Gt : out  STD_LOGIC;            Lt : out  STD_LOGIC); end compare_4; architecture Behavioral of compare_4 is begin Eq <= '1' WHEN A = B ELSE '0' ; Gt <= '1' WHEN A > B ELSE '0' ; Lt <= '1' WHEN A < B ELSE '0' ; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Compare_4_tb IS END Compare_4_tb;   ARCHITECTURE behavior OF Compare_4_tb IS        -- Component Declaration for