SR Flip-flop with Asynchronous Preset and Clear inputs

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 The VDHL Design implements SR flip-flop with Asynchronous Preset and Clear inputs. Asynchronous inputs Preset and Clear are active LOW input signals.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SR_FF is
    Port ( S,R,CLK,PR,CLR : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end SR_FF;
architecture Behavioral of SR_FF is
begin
process(S,R,CLK,PR,CLR)
 variable temp : std_logic;
 begin
 if(PR='0') then
 temp := '1';
 elsif(CLR='0') then
 temp := '0';
 elsif(CLK'EVENT and CLK='1') then
 if(R='0' and S='0') then
 temp := temp;
 elsif(R='1' and S='1') then
 temp := 'Z';
 elsif(R='1' and S='0') then
 temp := '0';
 else
 temp := '1';
 end if;
 end if;
 Q <= temp;
 end process;
end Behavioral;


Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY SR_FF_Tb IS
END SR_FF_Tb;
 
ARCHITECTURE behavior OF SR_FF_Tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SR_FF
    PORT(
         S : IN  std_logic;
         R : IN  std_logic;
         CLK : IN  std_logic;
         PR : IN  std_logic;
         CLR : IN  std_logic;
         Q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal S : std_logic := '0';
   signal R : std_logic := '0';
   signal CLK : std_logic := '0';
   signal PR : std_logic := '1';
   signal CLR : std_logic := '1';

  --Outputs
   signal Q : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: SR_FF PORT MAP (
          S => S,
          R => R,
          CLK => CLK,
          PR => PR,
          CLR => CLR,
          Q => Q
        );

   -- Clock process definitions
   CLK_process :process
   begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin
     PR <= '0'; wait for 10 ns;
  PR <= '1'; wait for 10 ns;
  
  R <= '1'; wait for 10 ns;
  R <= '0'; wait for 10 ns;
  
  CLR <= '0'; wait for 10 ns;
  CLR <= '1'; wait for 10 ns;
  
  S <= '1'; wait for 10 ns;
  S <= '0'; wait for 10 ns;

   end process;

END;


Output:

The above code is tested on Xilinx ISE Design Suite 14.7 Webpack.
It is intended only for educational purpose.

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