VHDL Design

 Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_Struct is     Port ( A,B : in  STD_LOGIC;            Diff, Borr : out  STD_LOGIC); end HS_Struct; architecture Behavioral of HS_Struct is component andgate is port(A,B : IN STD_LOGIC; Y: OUT STD_LOGIC); end component; component xorgate is port(A,B : IN STD_LOGIC; Y: OUT STD_LOGIC); end component; signal invA : STD_LOGIC; begin invA <= (not A); G1: xorgate port map(A=>A,B=>B,Y=>Diff); G2: andgate port map(invA,B,Borr); end Behavioral; VHDL Code for components: AND Gate VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xorgate is     Port ( A,B : in  STD_LOGIC; ...

Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_Behav is     Port ( A,B : in  STD_LOGIC;            Diff, Borr : out  STD_LOGIC); end HS_Behav; architecture Behavioral of HS_Behav is begin process(A,B) begin if(A='0' and B='0') then Diff <='0'; Borr <='0'; elsif(A='0' and B='1') then Diff <='1'; Borr <='1'; -- Diff=A-B; Borr=A-B elsif(A='1' and B='0') then Diff <='1'; Borr <='0'; elsif(A='1' and B='1') then Diff <='0'; Borr <='0'; else Diff<='Z'; Borr<='Z'; end if; end process; end Behavi...

Half Subtractor is a digital Circuit that subtracts two 1-bit number and returns two output signals, Difference and Borrow. The operation can be (A-B) or (B-A). The results will differ for these two operations. The following VHDL code is written for (A-B). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS_DF is     Port ( A,B : in  STD_LOGIC;            Diff,Borr : out  STD_LOGIC); end HS_DF; architecture Behavioral of HS_DF is begin Diff <= A xor B; Borr <= (not A) and B; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY HS_tb IS END HS_tb;   ARCHITECTURE behavior OF HS_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT HS_DF     PORT(          A : IN  std_logic;          B : IN  std_logic;          Diff : OUT...

The Half Adder circuit in Digital Electronics is used to add two 1-bit numbers and the circuit generates Sum and Carry as the outputs of this operation. The VHDL code for Half Adder circuit is written with structural modelling by using  andgate  and  xorgate  as components.   VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA_DF is     Port ( A,B : in  STD_LOGIC;            Sum, Carry : out  STD_LOGIC); end HA_DF; architecture Dataflow of HA_DF is begin Sum <= A xor B; Carry <= A and B; end Dataflow; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY HA_tb IS END HA_tb;   ARCHITECTURE behavior OF HA_tb IS        -- Component Declaration for the Unit Under Test (UUT)       COMPONENT HA_DF     PORT(          A : IN  std_logic;          B : IN  std_logic;    ...