VHDL Design

The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using with-select-when  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux is     Port ( Din : in  STD_LOGIC;            Dout : out  STD_LOGIC_VECTOR (3 downto 0);            Sel : in  STD_LOGIC_VECTOR (1 downto 0)); end demux; architecture Behavioral of demux is begin with sel select Dout <= "000"&Din when "00", "00"&Din&'0' when "01", '0'&Din&"00" when "10", Din&"000" when "11", "XXXX" when others; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY Demux_tb IS END Demux_tb;

  The demultiplexer is a combinational logic circuit designed to switch one input line to one of several separate output lines. It is exactly opposite of Multiplexer. In 1-to-4 Demux the input line is connected to one of the 4 output lines depending on the select line input. The below VHDL code is written using  if-else  statement. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux14 is     Port ( Din : in  STD_LOGIC;            Sel : in  STD_LOGIC_VECTOR (1 downto 0);            dout : out  STD_LOGIC_VECTOR (3 downto 0)); end demux14; architecture Behavioral of demux14 is begin process(din,sel) begin if(sel="00") then dout <= "000"&din; elsif(sel="01") then dout <= "00"&din&'0'; elsif(sel="10") then dout <= '0'&din&"00"; else dout <= din&"000"; end if; end process; end Behavioral; Testbench: LIBRARY ie

  The  4-to-1 Multiplexer is used to select between multiple input lines based on select line. The below code is written using  if-else  statement (sequential statement). VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux41 is     Port ( i0,i1,i2,i3,s0,s1 : in  STD_LOGIC;            Y : out  STD_LOGIC); end Mux41; architecture Mux41 of Mux41 is begin process(i0,i1,i2,i3,s0,s1) begin if(s1='0' and s0='0') then Y <= i0; elsif(s1='0' and s0='1') then Y <= i1; elsif(s1='1' and s0='0') then Y <= i2; elsif(s1='1' and s0='1') then Y <= i3; else  Y <= 'Z'; end if; end process; end Mux41; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY mux41_tb IS END mux41_tb;   ARCHITECTURE behavior OF mux41_tb IS      COMPONENT Mux41     PORT(          i0 : IN  std_logic;          i1 : IN  std_logic;          i2 : IN  std_logic;          

The 1-bit Full Adder circuit is used for adding two 1-bit numbers along with carry, if any, and generates two outputs viz. Sum and Carry. VHDL Code: (Dataflow) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin Sum <= A xor B xor Cin; Carry <= (A and B) or (B and Cin) or (A and Cin); end Behavioral; VHDL Code: (Behavioral) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is     Port ( A,B,Cin : in  STD_LOGIC;            Sum,Carry : out  STD_LOGIC); end FA_DF; architecture Behavioral of FA_DF is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0') then Sum <= '0'; Carry <='0'; elsif(A='0' and B='0' and Cin='1') then Sum <= '1'; Carry <='0'; elsif(A='0' and B='1' and Cin='0') then Su