VHDL Design

A sequence detector is a sequential circuit that outputs '1' when a particular pattern of bits sequentially arrives at its data input. A sequence detector typically has 1-bit Data Input, CLOCK Input and RESET Input. It generates 1-Bit Output. In this design, circuit receives input at W, generates output on Z. Every change occurs on Positive clock. The design detects occurrence of '1011' (non-overlapping) in the input sequence and produces output '1' after successfully detecting the sequence. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mealy_1011 is     Port ( W, clk, reset : in  STD_LOGIC;            z : out  STD_LOGIC); end Mealy_1011; architecture Behavioral of Mealy_1011 is type state_type is (a,b,c,d); signal Y : state_type; begin process(clk,reset) begin if(reset ='1') then Y <= A; ELSIF(RISING_EDGE(CLK)) THEN CASE Y IS WHEN A => IF(W='0') THEN y <= A; z ...

In PISO type shift register, the data is given as input to all the flip-flops at the same time (simultaneously), and the circuit will produce the serial output. In the VHDL Code Pin: Parallel Input CLR: clear input (or RESET input) CLK: clock input L_S: Load/Shift signal, used to control whether to load the Shift register with new data on Pin (i.e. L_S='1')  or to shift the existing data in the Shift register (i.e. L_S='0'). Sout: Output Signal VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Left_SR is     Port ( Pin : in  STD_LOGIC_VECTOR (7 downto 0);            clr, clk, L_S : in  STD_LOGIC;            sout : out  STD_LOGIC); end Left_SR; architecture Behavioral of Left_SR is signal temp: std_logic_vector(7 downto 0); begin process(clk,clr) begin if(clr='1') then temp <= "00000000"; elsif (clk'event and clk='1') then if(L_S='1') then temp <=...