SR Flip-flop with Asynchronous Preset and Clear inputs
The VDHL Design implements SR flip-flop with Asynchronous Preset and Clear inputs. Asynchronous inputs Preset and Clear are active LOW input signals. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SR_FF is Port ( S,R,CLK,PR,CLR : in STD_LOGIC; Q : out STD_LOGIC); end SR_FF; architecture Behavioral of SR_FF is begin process(S,R,CLK,PR,CLR) variable temp : std_logic; begin if(PR='0') then temp := '1'; elsif(CLR='0') then temp := '0'; elsif(CLK'EVENT and CLK='1') then if(R='0' and S='0') then temp := temp; elsif(R='1' and S='1') then temp := 'Z'; elsif(R='1' and S='0') then temp := '0'; else temp := '1'; end if; end if; Q <= temp; end process; end Behavioral; Testbench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SR_FF_Tb IS END SR_FF_Tb; ARCHI...