VHDL Design

1-bit Full subtractor subtracts two 1-bit numbers along with previous borrow, if any. In the following design A and B are the Two input numbers with C as borrow. The VHDL Code uses Structural Modeling with Basic Gates as components. VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FS is     Port ( A,B,C : in  STD_LOGIC;            Diff,Borr : out  STD_LOGIC); end FS; architecture Behavioral of FS is component andgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component orgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component xorgate is port(A,B : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; component notgate is port(A : IN STD_LOGIC; Y : OUT STD_LOGIC); end component; signal X1,n1,a1,a2,a3,o1 : STD_LOGIC; begin      g1:xorgate port map(A,B,x1);      g2:xorgate port map(x1,c,Diff);    ...